Hao Zheng is a tenure-track assistant professor in the Department of Electrical and Computer Engineering at the University of Central Florida.
Hao Zheng received his Ph.D. degree from George Washington University, advised by Prof. Ahmed Louri. He received his B.S. in Electrical Engineering from Beijing Jiaotong University, China. His research interests are in the areas of computer architecture, with emphasis on on-chip interconnects, energy-efficient many-core architecture designs, and machine learning for efficient computing.
Graduate Research Assistantships (GRAs) are available for Ph.D. students to work on several research projects include, but not limited to: machine learning techniques for efficient computing; heterogeneous chiplet-based architectures; application-aware reconfigurable manycore architectures; graph processing and neural network accelerators.
I am also hiring master and undergraduate research assistants at UCF.
If you are interested, please send your CV and Transcripts to Hao.Zheng@ucf.edu
03/2023 One Paper is Accepted in GLSVLSI'23.
03/2023 One Paper is Accepted in ISCA'23.
02/2023 One Paper is Accepted in DAC'23.
12/2022 Our group members, Chase and John, received AMD fellowship to support their research projects. Congrats!!!
11/2022 Two Patents (US 11502934,US 11489788 ) have been granted by USPTO.
10/2022 We received an equipment donation from Xilinx. Thank you Xilinx!
06/2022 We received a research grant from L3Harris, a leading aerospace and defense technology innovator. Thank you L3Harris!
[DAC'23] Jiaqi Yang, Hao Zheng, and Ahmed Louri, “Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications,” to appear in Proceedings of 60th Design Automation Conference (DAC’23), San Francisco, July 9-13, 2023.
[ISCA'23] Jiajun Li, Yuxuan Zhang, Hao Zheng, and Ke Wang, “ FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations,” to appear in Proceedings of 50th International Symposium on Computer Architecture (ISCA'50), Orlando, FL, June 17–21, 2023.
[GLSVLSI'23] Lingxiang Yin, Jun Wang, and Hao Zheng, “Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework,” to appear in Proceedings of 33rd ACM Great Lakes Symposium on VLSI (GLSVLSI), June 5-7, 2023.
[FCCM'23] Sanjay Gandham, Lingxiang Yin, Hao Zheng, and Mingjie Lin, “Poster: OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference,” to appear in Proceedings of 31st IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM), Marina Del Rey, CA, May 8-11, 2023.
[TCAS-I] Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth, ``ASCEND: A Scalable and Energy-Efficient DNN Accelerator with Photonic Interconnects", IEEE Transactions on Circuits and Systems I: Special Issue on Circuits and Systems for Emerging Computing Paradigms, April 2022.
[GLSVLSI'22] Jiaqi Yang, Hao Zheng, and Ahmed Louri, "Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation," in Proceedings of 32rd ACM Great Lakes Symposium on VLSI (GLSVLSI), June 6-8, 2022.
[DATE'22] Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, and Ahmed Louri, "AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems," in Proceedings of 25th Design, Automation & Test in Europe Conference (DATE), Mar. 14-23, 2022.
[TPDS] Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri, ''SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator with Workload Balancing", IEEE Transactions on Parallel and Distributed Systems (TPDS): Special Section on Parallel and Distributed Computing Techniques for AI, ML, and DL, 2021.
[TSUSC] Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri, "SecureNoC: A Learning-enabled, High-performance, Energy-efficient, and Secure On-chip Communication Framework Design", Accepted for Publication, IEEE Transactions on Sustainable Computing, 2021.
[HPCA'21] Hao Zheng, Ke Wang, and Ahmed Louri, "Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architecture", in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA'21), Seoul, South Korea, Feb. 27 - Mar. 3, 2021.
[DAC'20] Hao Zheng, Ke Wang and Ahmed Louri, “A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures,” in Proceedings of 57th Design Automation Conference (DAC’20), Virtual Conference, July 19-23, 2020.
[TETC] Hao Zheng, and Ahmed Louri, “Agile: A Learning-enabled Power and Performance-Efficient Network-on-Chip Design,” IEEE Transactions on Emerging Topics in Computing (TETC), DOI: 10.1109/TETC.2020.3003496, June 2020.
[IEEE Micro] Ke Wang, Hao Zheng and Ahmed Louri, “TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-On-Chip Architecture,” IEEE Micro, Special Issue on Machine Learning for Systems, Sept/Oct. 2020.
[DAC'19] Hao Zheng and Ahmed Louri, “An Energy-Efficient Network-on-Chip Design using Reinforcement Learning,” in Proceedings of 56th Design Automation Conference (DAC’19), Las Vegas, NV, June 2-6, 2019.
[CAL] Hao Zheng and Ahmed Louri, "EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable On-chip Interconnect." IEEE Computer Architecture Letters (CAL), no. 1, 88-91, 2018.
Hao Zheng and Ahmed Louri, "EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs.", U.S. Patent, US 11502934 B2, Granted, Nov. 2022
Hao Zheng, Ke Wang, and Ahmed Louri,, "A Versatile and Flexible Interconnection Network Design for Chiplet-Based Manycore Architecture", U.S. Patent, US 11489788 B2, Granted, Nov. 2022
Hao Zheng and Ahmed Louri, “A Learning-Enabled Energy-Efficient On-Chip Interconnection", U.S. Provisional Application No. 62/853,418, filed May, 2019.
Ke Wang, Hao Zheng, and Ahmed Louri, “Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework”, No. 63/019,720, U.S. Provisional Patent, filed May 2020.
Conference Organization: Finance Chair, ISCA'23; Local Arrangement Co-Chair, IPDPS'23; Web Chair, HPCA'19;
Program Committee: SRF@ASP-DAC'2023; IPDPS'2023; NAS'2022; HiPC'2022;
Conference Reviewer/Sub-reviewer: NoCs'2017-2019; ICCD'2018; ISCA'2021,2022; HPCA'2018,2020,2021;
Journal Reviewer: ACM/IEEE Transactions on Networking; IEEE Transactions on Sustainable Computing; IEEE Transactions on Computers; IEEE Micro; IEEE Transactions on Cloud Computing; IEEE Transactions on Circuits and Systems II;
ECE Best Dissertation Award, GWU, 2022
Best Paper Finalist, Design Automation Conference, 2020
First Place in ECE, SEAS R&D Showcase, 2019
First Place in the Engineering Category, GWU Research Days, 2019
NSF GW I-Corps Site Grant Award, 2019
Dean Summer Award Fellowship, 2018
Second Place in the Engineering Category, GWU Research Days, 2018
Phillip/Temofel Sprawcew Endowment Scholarship, 2017
High Academic Performance Award, 2016