Publications

[DAC'23] Jiaqi Yang, Hao Zheng, and Ahmed Louri, “Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications,” to appear in Proceedings of 60th Design Automation Conference (DAC’23), San Francisco, July 9-13, 2023.

[ISCA'23] Jiajun Li, Yuxuan Zhang, Hao Zheng, and Ke Wang, “ FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations,” to appear in Proceedings of 50th International Symposium on Computer Architecture (ISCA'50), Orlando, FL, June 17–21, 2023.

[GLSVLSI'23] Lingxiang Yin, Jun Wang, and Hao Zheng, “Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework,” to appear in Proceedings of 33rd ACM Great Lakes Symposium on VLSI (GLSVLSI), June 5-7, 2023.

[FCCM'23] Sanjay Gandham, Lingxiang Yin, Hao Zheng, and Mingjie Lin, “Poster: OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference,” to appear in Proceedings of 31st IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM), Marina Del Rey, CA, May 8-11, 2023.

[TCAS-I] Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth, ``ASCEND: A Scalable and Energy-Efficient DNN Accelerator with Photonic Interconnects", IEEE Transactions on Circuits and Systems I: Special Issue on Circuits and Systems for Emerging Computing Paradigms, April 2022.

[GLSVLSI'22] Jiaqi Yang, Hao Zheng, and Ahmed Louri, "Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation," in Proceedings of 32rd ACM Great Lakes Symposium on VLSI (GLSVLSI), June 6-8, 2022.

[DATE'22] Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, and Ahmed Louri, "AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems," in Proceedings of 25th Design, Automation & Test in Europe Conference (DATE), Mar. 14-23, 2022.

[TPDS] Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri, ''SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator with Workload Balancing", IEEE Transactions on Parallel and Distributed Systems (TPDS): Special Section on Parallel and Distributed Computing Techniques for AI, ML, and DL, 2021.

[TSUSC] Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri, "SecureNoC: A Learning-enabled, High-performance, Energy-efficient, and Secure On-chip Communication Framework Design", Accepted for Publication, IEEE Transactions on Sustainable Computing, 2021. 

[HPCA'21] Hao Zheng, Ke Wang, and Ahmed Louri, "Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architecture", in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA'21), Seoul, South Korea, Feb. 27 - Mar. 3, 2021.

[DAC'20] Hao Zheng, Ke Wang and Ahmed Louri, “A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures,” in Proceedings of 57th Design Automation Conference (DAC’20), Virtual Conference, July 19-23, 2020.

[TETC] Hao Zheng, and Ahmed Louri, “Agile: A Learning-enabled Power and Performance-Efficient Network-on-Chip Design,” IEEE Transactions on Emerging Topics in Computing (TETC), DOI: 10.1109/TETC.2020.3003496, June 2020.

[IEEE Micro] Ke Wang, Hao Zheng and Ahmed Louri, “TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-On-Chip Architecture,” IEEE Micro, Special Issue on Machine Learning for Systems, Sept/Oct. 2020.

[DAC'19] Hao Zheng and Ahmed Louri, “An Energy-Efficient Network-on-Chip Design using Reinforcement Learning,” in Proceedings of 56th Design Automation Conference (DAC’19), Las Vegas, NV, June 2-6, 2019.

[CAL] Hao Zheng and Ahmed Louri, "EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable On-chip Interconnect." IEEE Computer Architecture Letters (CAL), no. 1, 88-91, 2018.